1. Field of the Invention
This invention relates to a data processing system, and more particularly to a data processing system which stores an executing program in a main memory when the system calls a subroutine or has an interruption and which upon completion of the subroutine or interruption restores the executing program which is then continued.
2. Description of the Prior Art
In the present data processing systems, a central processing unit stores in a system main memory information according to what stage the executing program is in when the program calls a subroutine or when the executing program is interrupted. The information which should be saved for some time is, for instance, an address to which the program should return as designated by a program counter, a program status word (PSW) having a condition code, and the contents of a general purpose register. Especially, in the case of a program interruption, there is much information to be saved for a period of time because the system control changes from the executing program to a subroutine program when the interruption occurs.
In general, the data processing system will not immediately accept the interruption but will inhibit the interruption for sometime. The data processing system has a flag for inhibiting the interruption, which indicates whether the interruption will be accepted or not. The flag is set and reset by instructions and is saved for a period of time as a part of the program status word (PSW) in the main memory. An instruction calls the subroutine or the interruption, and then the program status word is restored from the main memory by a return instruction.
Referring to FIG. 1 through FIG. 4, a data processing system of the prior art is shown. In FIG. 1a the format of the PSW is explained. The PSW has a program counter (PC) portion to indicate the address of the execution instruction, a condition code flag (CC) portion and an inhibit mode flag for an interruption (IHF) portion. In FIG. 1b the PSW has two bits of information for an interruption inhibit level (IHL). The data processing system using the PSW shown in FIG. 1b controls the interruptions which are assigned a priority level. If the interruption has a priority level above the priority level identified by IHL, it is accepted. Otherwise, it is refused if the priority level of the interruption is below the priority level identified by the IHL. In FIGS. 2a and 2b there is shown a circuit which decides whether or not there is a request for an interruption. FIG. 2a shows a circuit for the PSW shown in FIG. 1a and FIG. 2b shows a circuit for the PSW shown in FIG. 1b. In FIG. 2a, there is formed the logical product of the interruption inhibit mode flag signal 11 from the PSW which is inverted by the inverter 13 and the interruption request signal 12 by means of the AND gate 14. For instance, if the interruption inhibit mode flag signal 11 is "0" and the interruption request signal 12 is "1", the AND gate 15 outputs a "1" accepting the interruption request. FIG. 2b shows the interruption request signals 22a, 22b, and 22c with respective priority levels 1, 2 and 3, and the interruption inhibit level outputs 21a and 21b from the PSW. A decoder 23 outputs "1" from only one of its outputs 24a-24d in response to the interruption inhibit levels 0-3. In accordance with the logical circuit as shown in FIG. 2b the output 25 signifies the existence of an interruption request to be accepted according to the following table:
TABLE ______________________________________ Interruption Inhibit Interruption Request Level Level Output 23a 21b 22a 22b 22c 25 ______________________________________ X X 0 0 0 0 0 0 1 X X 1 0 0 X 1 X 1 0 0 X X 1 1 0 1 X 0 0 0 0 1 X 1 X 1 0 1 X X 1 1 1 0 X X 0 0 1 0 X X 1 1 1 1 X X X 0 ______________________________________
When the program which had been interrupted returns, the CPU continues to execute the program by restoring the information which was saved during the interruption from the main memory. The CPU upon accepting an interruption usually changes its processing control to an inhibit mode in which any further interruptions are inhibited until after the accepted interruption is completed. Thus just prior to restoring the executing program, the CPU usually operates in the inhibit mode to inhibit further interruptions. In the case where a first interruption occurs, there is a great possibility that a second interruption must wait for the first interruption to be completed. The CPU releases itself from the interruption inhibiting state by restoring the PSW with the return instruction. The CPU again accepts another interruption and changes its process control to another interruption program only after it saves its present state in the main memory. Therefore, there is an inefficiency in storing again the information which was just restored.
FIG. 3 shows a flow chart for operation when an interruption occurs. The step 31 tests whether a request for an interruption may be accepted or not. Namely, the step 31 tests the level of the signal 15 or the signal 25 and determines whether the CPU is in the inhibit mode. If there is no request for an interruption, the step 32 reads the instructions designated by the program counter and performs the instruction. If there is a request for an interruption and it is not inhibited, step 35 stores information for some time in the main memory, such as the program status word (PSW) having the program counter portion and the inhibit bit for the interruption, and such as the contents of the general purpose register in the CPU. The information is stored at a location designated by the stack pointer. The stack pointer will be revised to designate the next location. This operation is called "PUSH".
FIG. 4 shows the return instruction to return to the original program from the interruption processing program. FIG. 4 only shows the step 41 corresponding to the step 35 in FIG. 3. The return instruction reverses the operation of step 35. Namely, the return instruction reads the PSW and the contents of the general purpose register from main memory as addressed by the stack pointer, and restores them into their corresponding CPU registers. The stack pointer will be revised to designate former stack location. This operation is called "POP". The operation following the end of the return instruction is the start point in FIG. 3. Therefore, if a new interruption request can be accepted by the designation of a restored PSW, the step 35 performs the PUSH operation again.